Registered outputs for memory devices as provided in the past utilize a data storage device between the output of the memory sense amplifier and the output driver stage of the memory. This storage device, commonly a latch circuit, requires a clock signal supplied to the memory device to load data from the sense amplifier into the latch.
However, certain standards have developed in the industry with respect to the number of pins in an integrated circuit package and the functions of each of these pins, and the requirement of an external clock signal necessitates a nonstandard package for the memory device. Moreover, additional pins require a larger package and more room on a printed circuit board for routing additional signals to the integrated circuit package.
Also relevant to the present invention is the access time of conventional memory devices. The access time specified by manufacturers is the time in which the output data at the output pin of the integrated circuit is transitioning to a logical 0 level or a logical 1 level. Therefore, the data is available to the user actually at a later time, the time required for the output signals from the memory to be stable long enough to enable the circuitry inside the device being driven by the memory to stabilize and reliably detect the output signal from the memory device. Moreover, the output of the sense amplifier inside the memory device is generally several nanoseconds faster than the time the output data is available at the output pin of the memory device due to the delay through the output driver circuit of the memory device and the capacitance associated with the output pin and circuitry being driven by the memory device. Stated another way, the data at the output of the sense amplifier of the memory device is available several nanoseconds before the data can be reliably transferred from the output pin of the memory device to the circuit receiving the data.
Therefore, it can be appreciated that registered output circuitry for a memory device which is able to store the output data from the memory device without necessitating an external clock signal and which is also able to decrease the average access time of the memory device by effectively eliminating the delays occurring after the data is present at the output of the sense amplifier is highly desirable.